Half-bridge gate driver circuit

ABSTRACT

A half-bridge gate driver circuit including two separate floating high-side driver circuits for operating a switch circuit having a high-side switch and a low-side switch. Each of the driver circuits include input control logic which is referenced to a supply signal with a potential that becomes negative relative to the negative common terminal of the switches, thereby enhancing the operation of the switch circuit. The circuit may further include signal translation stages for translating control signals to the control logic of the driver circuits. The signal translation stages include a plurality of cascoded parasitic transistors which provide a neutralizing capacitance to minimize noise.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to switch-mode, half-bridge powercircuits using gated devices, and, more particularly, to opposedcurrent, power converter circuits driven by integrated circuit gatedrivers with internal floating gate driver sections.

[0003] 2. Description of the Related Art

[0004] Modern half-bridge power circuits are frequently driven byintegrated circuit (IC) gate drivers with internal floating gate driversections driving the more positive voltage high-side of the half-bridge.The high-side and low-side input control signals are supplied common tothe most negative portion of the IC. When IC gate drivers are used inhigh-voltage, hard-switching, half-bridge power converters, a problemcan arise at the turn-off of the positive voltage high-side switch ofthe half-bridge. In this situation, the instantaneous voltage on thesource lead of the high-side switch can momentarily go negative relativeto the negative substrate of the IC. The principal reason for thevoltage spike is that in a hard-switching converter, the free-wheelingdiode cannot become fully conductive instantaneously. The free-wheelingdiode's forward voltage can thus become rather large during this timedelay compared to what would be expected in the DC case. In thetransient case, the diode appears as a very high resistance device andmay have 20 volts forward-biased across it. The 20 volt forward bias maylast for approximately 10 to 20 nanoseconds until the diode becomesfully injected. The result is that the gate drive voltage goes negativewith respect to the negative substrate of the IC with 20 volts plus anyadditional voltage due to inductance. As a result, the IC may cause amalfunction of the driver logic resulting in failure of the power stageby simultaneous conduction of the power switches or direct destructionof the gate driver IC. At a minimum, noise will be introduced into thesystem.

[0005] Methods have been developed to attempt to correct this problem.One method attempts to reduce the added voltage generated by theintrinsic inductance in the circuit, thereby decreasing the negativevoltage spike imposed on the IC at the turn-off of the positive switch.This method has a serious drawback in the field of the presentinvention. Even if a designer were to compensate for all inductances inthe construction of the circuit, the transient forward voltage acrossthe free-wheeling diode would still be present in the circuit.Attempting to compensate for the intrinsic inductance in the circuitfails to provide a successful solution in fast-switching, high-frequencyapplications since the forward voltage produced by the free-wheelingdiode will still cause simultaneous conduction of the power switches ordirect destruction of the gate driver IC.

[0006] Another problem of conventional designs is that they have aslower high-side gate driver due to the increased number of cascadedstages in the high-side gate driver as compared to the low-side gatedriver. Some designs attempt to match the propagation delay between thehigh-side and low-side outputs by adding delays in the low side path. Atypical method of adding such delays is to cascade an even number ofinverters. Despite this effort, the result of the increased number ofcascaded stages is imprecise timing in the circuit resulting incommon-mode currents or shoot-through. The imprecise timing becomesparticularly problematic when attempting to maintain timing over bothtime and temperature variations. Tolerances of the power switches, gatedrive resistors, temperature thresholds, imperfections of the IC, andother parameters must be accounted for. When the tolerances are loose,increased distortion occurs in certain applications, for example,pulse-width modulated (PWM) audio amplifiers.

SUMMARY OF THE INVENTION

[0007] The present invention provides a circuit for minimizing theeffects on gate driver ICs of high-voltage, hard-switching such as whendriving opposed current power converters and other similar applications.The present invention overcomes the shortcomings of the prior art byutilizing two separate high-side gate drivers to drive an opposedcurrent power converter, as opposed to the conventional, singlehigh-side gate driver together with a low-side gate driver.

[0008] The invention, in one form thereof, comprises a switch-modeopposed current power converter with two separate floating high-sidegate drivers. The removal of the low-side driver from the circuitpermits the negative substrate potential of the IC to be as negative asnecessary to protect the IC. The result is maximum isolation between thecontrol signals for desired applications. The isolation between thecontrol signals reduces the harmful effect of noise generated by thetransition of one switch on the modulation process of another switch.The isolation benefits gained by the present invention allow for asingle IC to incorporate multiple high-side gate drivers. The presentinvention has various applications including, for example, audioamplifiers and three-phase motors which require an IC with six high-sidegate driver stages.

[0009] The high-side design construction operates both the high-side andlow-side switches with input control logic referenced to a supply with anegative substrate potential which, in operation, becomes negative withrespect to the negative common terminal of both power switches. Ineffect, the negative substrate potential will be as negative as the mostnegative spike of forward voltage produced by the free-wheeling diode atthe turn-off of the positive switch, thereby preventing a malfunction ofthe driver logic and destruction of the gate driver IC.

[0010] The input control logic reference supply voltage can be producedfrom a variety of sources. A battery could provide the necessaryvoltage, although this adds complexity and cost to the system. In oneexemplary embodiment, the reference supply voltage is acquired bymanipulating the forward recovery voltage of the free-wheeling diode toobtain the necessary voltage required to protect the IC. In anotherembodiment, the input control logic supply voltage is acquired by theuse of an AC power supply already present in the circuit. Theabove-described embodiments provide the necessary voltage to the inputcontrol logic without increasing cost or introducing the addedcomplexity associated with an extra power supply.

[0011] In one embodiment of the present invention, a signal translationstage may be included to provide a front-end scheme of translating theinput signals to the control logic of the gate drivers. The signaltranslation stage can be used to correct for noise issues associatedwith the input signals to the control logic of the gate drivers. Thecompensation of the signal translation stage is equally useful incorrecting noise issues whether they originated on the negative supplyvoltage (−V_(cc)) or were a product of the derived reference supplyvoltage (−V_(cx)) as further derived below. A signal translation stageincludes three or more cascaded transistors with the associated bypasscapacitors and resistors to more easily dissipate the noise incident onthe control logic from the input signals. Also included in the signaltranslation stage are parasitic transistors which form the appropriatenonlinear capacitance to track voltages in the cascaded chain, and toproperly cancel the effects of noises on the −V_(cx) supply. Thetransistors utilized in the construction of the signal translation stageinclude, but are not limited to, those shown in the drawings. Oneskilled in the art could readily adapt other types of transistors to thepresent application. An exemplary embodiment of the signal translationstage is a unique type of high-side gate driver IC which translates thesignal from ground to the negative potential of the −V_(cx) supply.

[0012] An advantage of the present invention is that it permits anegative voltage spike on the source lead of the high-side power switchwithout risking the dysfunction of the converter or other damage to theIC.

[0013] Another advantage of the present invention is that the symmetricdesign allows the propagation delays of the IC to be more uniform forboth the high-side and low-side power switches.

[0014] Still another advantage of the present invention is theminimization of the quiescent output ripple for an interleavedconverter.

[0015] A still further advantage of the present invention is a morecomplete isolation of the input from the output of the driver, therebyreducing noise incident on the input.

[0016] Yet another advantage of the present invention is themaximization of the drain source voltage on the internal gate drivertranslating field effect transistors, thereby reducing the propagationdelay of the high-side driver.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above-mentioned and other features and advantages of thisinvention, and the manner of attaining them, will become more apparentand the invention itself will be better understood by reference to thefollowing description of embodiments of the invention taken inconjunction with the accompanying drawings, wherein:

[0018]FIG. 1 is a schematic diagram of a prior art circuit including ahigh-side gate driver and a low-side gate driver;

[0019]FIG. 2 is a schematic diagram of two separate high-side gatedrivers and an independent negative substrate potential which suppliesthe input control logic of the ICs;

[0020]FIG. 3 is a schematic diagram of two separate high-side gatedrivers and a circuit for deriving the independent negative substratepotential (−V_(cx)) which supplies the input control logic of the ICs;

[0021]FIG. 4 is a schematic diagram of two separate high-side gatedrivers and another embodiment of a circuit for deriving −V_(cx); and

[0022]FIG. 5 is a schematic diagram of two separate high-side gatedrivers, a circuit for deriving −V_(cx), and a signal translation stage.

[0023] Corresponding reference characters indicate corresponding partsthroughout the several views. The exemplifications set out hereinillustrate embodiments of the invention and such exemplifications arenot to be construed as limiting the scope of the invention in anymanner.

DETAILED DESCRIPTION OF THE INVENTION

[0024] Referring now to the drawings, FIG. 1 illustrates a prior artopposed current power converter 11. The PWM signals are input into thelow-side driver circuit 6 after passing through low-side input signaltranslator transistor 40 and into the high-side circuit 8 driver afterpassing through high-side input signal translator transistor 42. Theinput signals communicate with high-side switch 7 and low-side switch 9to produce on and off conditions. The input signal for high-side switch7 is received by Schmitt trigger 10 which provides robustness to thelogic to make it less sensitive to noisy input signals. NOR gate 18receives output signals from Schmitt trigger 10 and undervoltage device20. Undervoltage device 20 functions as an interlock by defeating thedrive signal if too little voltage is present. Pulse generator 26 turnson or off in response to a high or low output from NOR gate 18. Pulsegenerator 26 provides an alternating pulse signal first to translatingfield effect transistor 27 and then to translating field effecttransistor 25. The outputs from translating field effect transistors 25,27 are sent to receiving stage 30 to set and then reset thecorresponding input pins on the flip-flop of receiving stage 30.Undervoltage device 28 is connected to the reset pin on receiving stage30, and functions as an interlock by defeating the drive signal if toolittle voltage is present. The output from receiving stage 30 is routedto high-side gate driver 32. High-side gate driver 32 is powered byvoltage V_(b) and voltage V_(s). The driving and inverted output fromhigh-side gate driver 32 typically produces one-half (½) to about three(3) amperes of drive. The drive output is fed through resistor R_(gp) todrive high-side switch 7.

[0025] The input signal for low-side switch 9 is similarly received bySchmitt trigger 12 connected to time delay block 22. Gate 24 receivesoutput signals from time delay block 22 and undervoltage device 20.Low-side gate driver 34 receives the output from gate 24. Low-side gatedriver 34 is powered by voltage V_(cc) 15 and is connected to the commonsignal of the IC. The driving and inverted output from low-side gatedriver 34 drives low-side switch 9 through resistor R_(gn).

[0026]FIG. 2 is a schematic diagram of an opposed current powerconverter driven by two separate high-side driver circuits 8, 8′ inaccordance with the present invention. The input signal for high-sideswitch 7 is received by Schmitt trigger 10. NOR gate 18 receives outputsignals from Schmitt trigger 10 and undervoltage device 20. Undervoltagedevice 20 functions as an interlock as described above. Pulse generator26 receives a high or low output from NOR gate 18 indicating when toturn on or turn off. Pulse generator 26 provides an alternating pulsesignal first to translating field effect transistor 27 and then totranslating field effect transistor 25. The outputs of transistors 25,27 are sent to receiving stage 30 to set and then reset thecorresponding input pins of the flip-flop of receiving stage 30.Undervoltage device 28 is connected to the reset pin on receiving stage30, and functions as an interlock as described above. The output fromreceiving stage 30 is routed to high-side gate driver 32, which ispowered by voltage V_(b) and voltage V_(s). The driving and invertedoutput from high-side gate driver 32 typically produces one-half (½) toabout three (3) amperes of drive. The drive output of driver 32 is fedthrough resistor R_(g) to drive high-side switch 7.

[0027] The input signal to high-side driver circuit 8′ for low-sideswitch 9 is translated through the identical logic as the input signalfor high-side switch 7. The drive output for low-side switch 9, however,is fed through resistor R_(g) to drive low-side switch 9.

[0028] Battery 48 produces voltage −V_(cx) 13 which supplies the inputcontrol logic reference voltage. The logic of the two high-side drivercircuits 8, 8′ is powered by a simple shunt regulator with Zener diode46, bypass capacitor 44, and resistor 52 connected to earth ground. Itshould be understood that the value of the voltage −V_(cx) 13 producedby battery 48 needs to be as negative as the greatest excursion, i.e.,most negative value, of the forward voltage across diode D_(p) 14. Also,it should be known that the common portion is a recitation of thevoltage through the diode 14.

[0029]FIG. 3 illustrates the use of two separate high-side drivercircuits 8, 8′ similar to that of FIG. 2 and represents anotherembodiment of a circuit for producing −V_(cx) 13. Diode D_(p) 14 isconnected to diode D₁. When a large forward voltage appears across diodeD_(p) 14 at the turn-off of high-side switch 7, diode D₁ begins toconduct because the voltage on the negative side of diode D₁, i.e., theside connected to diode D_(p) 14, is more negative than −V_(cc) 15. Oncediode D₁ begins to conduct, −V_(cx) 13 is pulled down the value of V_(s)during the transient excursion of switch 7. During this excursion,−V_(cx) 13 has a value which is V_(s) plus the turn-on voltage of diodeD₁. The result is that the voltage levels of −V_(cx) 13 and V_(s) arevery close to each other, and both voltages are more negative than−V_(cc) 15. Diode D₂ provides −V_(cx) 13 during quiescent conditionswhen the converter is not switching, thereby preventing problems to theIC when not in operation.

[0030]FIG. 4 illustrates the use of two separate high-side drivercircuits 8, 8′ as in FIG. 2 with an arbitrary AC voltage source 54 toproduce −V_(cx) 13. Source 54 is connected to capacitor C_(pump), whichin turn is connected to both diode D₁′ and diode D₂. Source 54 could begenerated by a separate AC generator or one of several small AC powersupplies present in a typical application circuit such as aswitched-mode power converter for audio applications. The dotted linesin FIG. 4 show two possible points of connection for source 54. Source54 should operate at the same frequency at which the entire circuit isoperating, or some harmonic thereof, to avoid undesirable beatfrequencies.

[0031] In operation, a current is produced through diode D₂ during thepositive voltage swing of source 54. Correspondingly, on the negativevoltage swing of source 54, diode D₁′ begins to conduct, thereby pulling−V_(cx) 13 down to V_(s) during the instantaneous excursion of thehigh-side switch.

[0032]FIG. 5 includes a signal translation stage 70 for processing theinput signals to the gate drivers. Signal translation stage 70 couldalso have been used with the circuits of FIGS. 1 through 4. Signaltranslation stage 70 comprises several, typically three or more, commonbase stages 71 cascoded together (i.e., the collector of one transistorof a stage 71 is connected to the emitter of the transistor of the nextstage 71). Each PWM switch enable signal travels through the emitter ofeach of its respective common base stages 71 and out the collector. In apractical embodiment, each stage 71 is a divider which is designed totranslate the PWM signals down from earth ground before they are inputinto high-side driver circuits 8, 8′. Several small stages 71 are usedto translate the large voltage on the input signals, since smalltransistors can only translate a portion of the large voltage. On theother hand, small transistors are beneficial because they have lowoutput capacitance.

[0033] Each stage 71 includes capacitors 60, 62 for noise reduction. Foreach additional stage not shown, more capacitors would be present toperform the same function. The base node of each transistor of the chainof stages 71 is bypassed to earth ground, except for translatingtransistors Q_(bn) and Q_(bp) which are tied to V_(cc) 15 throughresistors 64, 66, respectively. The AC noise incident from the PWMsignals exists across the base-collector junctions of translatingtransistors Q_(bn) and Q_(bp). Translating transistors Q_(bn) and Q_(bp)carry the current from the PWM signals, and are selected for minimumoutput capacitance. This permits a minimum disturbance to the collectorcurrent when noise is imposed between −V_(cx) 13 and earth ground.Parasitic transistors Q_(cn) and Q_(cp) are used to cancel the noisepresent in the collectors of translating transistors Q_(bn) and Q_(bp).

[0034] In operation, signal translation stage 70 of FIG. 5 produces acurrent that augments the current flow down through the chain such thata minimum voltage is induced across resistors R_(ip) and R_(in) due to achange in current. An inversion occurs in the voltage across resistorsR_(ip) and R_(in) because they are in series with the signal path. Inother words, if −V_(cx) 13 instantaneously goes more negative, thevoltages across resistors R_(ip) and R_(in) go positive with respect tothe input pins of buffers 56, 58, respectively. The voltages acrossresistors R_(ip) and R_(in) are literally out of phase with −V_(cx) 13.The net noise current seen by R_(ip) and R_(in) pollutes the signalswhich are incident on buffers 56 and 58. Buffers 56 and 58 arereferenced to −V_(cx) 13. This embodiment permits buffers 56 and 58 tocancel out the noise present at their inputs.

[0035] The noise voltage across translating transistors Q_(bn) andQ_(bp) is the same voltage that is desired to exist across thetransistors Q_(cn) and Q_(cp). Charging currents are fed back to thechain to cancel the noise in the base-collector capacitance oftranslating transistors Q_(bn) and Q_(bp). Translating transistorsQ_(bn) and Q_(bp), however, do not have the same operating point asparasitic transistors Q_(cn) and Q_(cp) because parasitic transistorsQ_(cn) and Q_(cp) have no current flow through them. The outputcapacitance of a transistor is slightly increased when current isflowing through it. Since current is flowing through translatingtransistors Q_(bn) and Q_(bp), but not through parasitic transistorsQ_(cn) and Q_(cp), the output capacitances of the transistors aredifferent. This is compensated by connecting the collectors of parasitictransistors Q_(cn) and Q_(cp) to −V_(cc) 15 because that forces theoutput capacitance of parasitic transistors Q_(cn) and Q_(cp) toincrease and compensates for their lack of carrying bias. With thiscompensation, parasitic transistors Q_(cn) and Q_(cp) form theappropriate nonlinear capacitance to track voltage in the array, and toproperly cancel the effects of noise from the −V_(cx) 13 supply line.

[0036] While this invention has been described as having a preferreddesign, the present invention can be further modified within the spiritand scope of this disclosure. This application is therefore intended tocover any variations, uses, or adaptations of the invention using itsgeneral principles. Further, this application is intended to cover suchdepartures from the present disclosure as come within known or customarypractice in the art to which this invention pertains.

1. A gate driver circuit for a half-bridge derived switching powerconverter having a positive switch coupled to a negative potential, anda negative switch coupled to the negative potential, the gate drivercircuit including: a first driver circuit for operating the positiveswitch; and a second driver circuit for operating the negative switch;whereby the first and the second driver circuits having a power inputand being referenced to a common potential which, during operation ofthe circuit, becomes negative relative to the negative potential.
 2. Thegate driver circuit set forth in claim 1 wherein the positive switchincludes a diode connected between an output of the positive switch andthe negative potential, the common potential being a rectification ofthe voltage through the diode.
 3. The gate driver circuit of claim 1wherein the common potential is provided by a charge pump referenced tothe negative potential and driven by an AC source.
 4. The gate drivercircuit of claim 1 further including a first and a second signaltranslation stage, the first and second signal translation stagestranslating a plurality of switch enabling signals from DC potentialsthat are positive relative to the common potential to input the switchenabling signals to the first and second driver circuits, respectively,each signal translation stage including a plurality of three-terminalsemiconductors, one of the semiconductors of the first signaltranslation stage having an input coupled through a capacitance to thepower input.
 5. The gate driver circuit of claim 4 further characterizedin that the capacitance is the output capacitance of another of thesemiconductors of the first signal translation stage.
 6. A gate drivercircuit for a half-bridge derived switching power converter having afirst switch coupled to a first and a second potential which define apotential range, and a second switch coupled to the first and the secondpotentials, the circuit including: a first driver circuit for operatingthe first switch; and a second driver circuit for operating the secondswitch; the first and the second driver circuits having a power inputand being referenced to a common potential which, during operation ofthe circuit, transitions outside the potential range.
 7. The gate drivercircuit of claim 6 further characterized in that the first switchincludes a diode connected between an output of the first switch and thefirst potential, the common potential being a rectification of thevoltage through the diode.
 8. The gate driver circuit of claim 7 whereinthe common potential is provided by a charge pump referenced to thenegative potential and driven by an AC source.
 9. The gate drivercircuit of claim 8 further including a first and a second signaltranslation stage, the first and second signal translation stagestranslating a plurality of switch enabling signals from DC potentialsthat are positive relative to the common potential to input the switchenabling signals to the first and second driver circuits, respectively,each signal translation stage including a plurality of three-terminalsemiconductors, one of the semiconductors of the first signaltranslation stage having an input coupled through a capacitance to thepower input.
 10. The gate driver circuit of claim 9 furthercharacterized in that the capacitance is the output capacitance ofanother of the semiconductors of the first signal translation stage. 11.A gate driver circuit for a half-bridge derived switching powerconverter having a positive switch coupled to a negative potential, anda negative switch coupled to the negative potential, the gate drivercircuit comprising a first driver circuit for operating the positiveswitch, a second driver circuit for operating the negative switch,whereby the first and the second driver circuits have a power inputwhich are referenced to a common potential.
 12. The gate driver circuitset forth in claim 11 wherein a positive potential wherein the positivepotential and the negative potential define a potential range, thecommon potential transitioning outside the potential range duringoperation of the circuit.
 13. The gate driver circuit set forth in claim11, whereby the common potential becomes negative relative to thenegative potential during operation of the gate driver circuit.
 14. Thegate driver circuit set forth in claim 13 further including a diodeconnecting the first switch and the negative potential.
 15. The gatedriver circuit set forth in claim 14 whereby the common potential is arectification of the voltage through the diode.
 16. The gate drivercircuit set forth in claim 15, whereby the common potential is providedby a charge pump referenced to the negative potential and drive by an ACsource.
 17. The gate driver circuit as set forth in claim 16 furtherincluding a signal translation stage, the signal translation stagetranslating a plurality of switch enabling signals from DC potentials,the potentials being positive to the common potential.
 18. The gatedriver circuit as set forth in claim 17, whereby each signal transitionstage includes a plurality of three-dimensional semiconductors, one ofthe semiconductors of the signal translation having an input coupledthrough a capacitance to the power input.
 19. The gate driver circuit asset forth in claim 18, whereby the capacitance is the output capacitanceof another of the semiconductors of the first signal translation stage.20. The gate driver circuit as set forth in claim 19, wherein the firstdriver circuit includes a Schmidt trigger, a NOR gate, and a pulsegenerator arranged to generate a signal to a plurality of transistorsallowing the first switch to be activated and deactivated in a softswitching manner.